The present invention relates to a testing system for an integrated circuit, and more specifically, to a testing system and related testing method for an analog design under test of an integrated circuit using a built-in processor to execute a program sequence without conditional jumps.
Please refer to FIG. 1. FIG. 1 shows a block diagram of a conventional analog testing system 100. Traditionally, to test a plurality of analog design under tests (DUTs) 102, 103 of an integrated circuit 104 (for example, a SOC design) requires an analog channel of an external test machine 101 electrically connecting analog DUTs and external test machine 101. Certainly, the performance of this kind of analog testing system 100 is limited due to a settle time required to stabilizing signals transmitted between external test machine 101 and the integrated circuit 104. For example, when starting a new test session, the settle time for this new test session increases the whole testing time. Moreover, resolution of the analog channel of external test machine 101 also plays an important role. Obviously, these issues are closely related to cost and price of the external test machine 101.
Please refer to FIG. 2. FIG. 2 shows a block diagram of a conventional analog testing system 200 with an external processor 201. As shown in FIG. 2, the analog testing system 200 includes an external processor 201 coupled to an integrated circuit 206, where the integrated circuit 206 has a plurality of analog design under tests (DUTs) 202, 203, a built-in digital-to-analog converter (DAC) 204, and a built-in analog-to-digital converter (ADC) 205. The analog testing system 200 tests analog design under tests 202, 203 with a built-in DAC 204 used to convert a digital testing sequence generated from the external processor 201 into analog domain and feed the converted signals into the analog design under tests 202, 203. Then, the built-in ADC 205 is utilized to convert a testing response of the analog design under tests 202, 203 into digital domain for further processing and determination. With the help of built-in ADC 205 and DAC 204, the settle time of the testing system 200 is substantially reduced. Moreover, cost of analog testing is lowered, accordingly.
As shown in FIG. 1 and FIG. 2, no matter using external test machine 101 or external processor 201, ADC 205 and DAC 204 for testing analog under tests 102, 103, 202, 203, it requires an analog signal generator and a measuring tool. Using DAC 204 and ADC 205 together with external processor 201 as the analog signal generator to generate test patterns and the measuring tool for analyzing test results respectively has many advantages. For instance, if a testing sequence, i.e. the output of the DAC 204, is changed or the measuring point, i.e. the input of the ADC 205, is altered, it will not induce any extra settle time for starting the corresponding analog testing procedure because DAC 204 and ADC 205 are built-in. Analog testing system 200 certainly reduces the operating time required for analog testing. However, to realize analog testing system 200 as mentioned above, in most case external processor 201 is generally implemented as a testing module of external test machine 101 as shown in FIG. 1 Cost of external processor 201 will certainly increase the cost of applying this kind of testing system.
Please refer to FIG. 3. FIG. 3 shows a block diagram of a conventional analog testing system 300 using an internal processor 301, built-in DAC 304, built-in ADC 305, together with an internal memory 306 and a program loader 308. Built-in DAC 304 and built-in ADC 305 are connected to analog design under test 302 and 303. As shown in FIG. 3, the analog testing system 300 has an integrated circuit 307 coupled to a program loader 308, where the integrated circuit 307 includes an internal processor 301, a plurality of analog design under tests (DUTs) 302, 303, a built-in digital-to-analog converter (DAC) 304, a built-in analog-to-digital converter (ADC) 305, and an internal memory 306. In this testing system 300, internal processor 301 plays the role as external processor 201 shown in FIG. 2 but has an advantage of reducing the cost of testing module of the external test machine by using a processor which is originally embedded in the integrated circuit 307. However, the analog testing system 300 needs extra efforts such as applying a processing program for controlling internal processor 301 to generate the testing sequence and to measure the testing response to make decision if the analog testing result is pass or fail. To this end, the processing program must be input to internal processor 301 in a form of program sequence. Moreover, since the processing program must do conditional logical operation to decide if the analog testing result is pass or fail, executable codes for doing the logical operation in all kinds of conditions must be preloaded into the internal memory 306 through the program loader 308 so that the processing program is able to do logical operation, such as perform an “if” condition or an “else” condition. For example, a program sequence PROGRAM—1 (only part of the program sequence is illustrated) with conditional jumps is shown as below:
Line1: int result; //0 means testing failure, 1 means testing pass
Line2: if (analog_measure—1 meet spec—1) {result=1;}
Line3: else {result=0;}
In PROGRAM—1, if a condition “analog_measure—1 meet spec—1 is true, then the program sequence will conditionally jump to “result=1” in Line2. Otherwise, if the condition is false, the program sequence will conditionally jump to “result=0” in Line3. For storing these two conditions in Line2 and Line3 previously, it requires more cost in internal memory 306 and time for preloading the program sequence PROGRAM—1 into the internal memory 306, which could possibly dominate the whole testing time. In short, doing analog testing with analog testing system 300 is not efficient enough because the program with conditional jump operations need to be loaded into internal memory 306 first.